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https://github.com/cnlohr/lolra.git
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cnlohr
586 lines
15 KiB
C
586 lines
15 KiB
C
/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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// XXX WARNING: Something is wrong with this -
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// The output isn't perfectly time aligned
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// And as such there are extra images in weird places.
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// TODO: Investigate the DMA+SPI Port jankyness.
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#include "ch32v003fun.h"
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#include <stdio.h>
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#include <string.h>
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#include "LoRa-SDR-Code.h"
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#define DMA_SIZE_WORDS 128
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#define SENDBUFF_WORDS (DMA_SIZE_WORDS*2)
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uint8_t sendbuff[SENDBUFF_WORDS];
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// Bits are shifted out MSBit first, then to LSBit
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#define MAX_BYTES 25
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#define MAX_SYMBOLS (MAX_BYTES*2+16)
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// Our table is bespoke for the specific SF.
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#define CHIPSSPREAD CHIRPLENGTH_WORDS// QUARTER_CHIRP_LENGTH_WORDS (TODO: Use the quater value elsewhere in the code)
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#define MARK_FROM_SF0 (1<<SF_NUMBER) // SF7
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#define PREAMBLE_CHIRPS 10
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#define CODEWORD_LENGTH 2
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uint32_t quadsetcount;
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int16_t quadsets[MAX_SYMBOLS*4+PREAMBLE_CHIRPS*4+9+CODEWORD_LENGTH*4];
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int runningcount_bits = 0;
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volatile int fxcycle;
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volatile int quadsetplace = -1;
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volatile uint32_t temp;
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static uint16_t lora_symbols[MAX_SYMBOLS];
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int lora_symbols_count;
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#if 0
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int16_t * AddChirp( int16_t * qso, int offset, int verneer )
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{
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offset = offset * CHIPSSPREAD / (MARK_FROM_SF0);
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offset += verneer;
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*(qso++) = (CHIPSSPREAD * 0 / 4 + offset + CHIPSSPREAD ) % CHIPSSPREAD;
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*(qso++) = (CHIPSSPREAD * 1 / 4 + offset + CHIPSSPREAD ) % CHIPSSPREAD;
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*(qso++) = (CHIPSSPREAD * 2 / 4 + offset + CHIPSSPREAD ) % CHIPSSPREAD;
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*(qso++) = (CHIPSSPREAD * 3 / 4 + offset + CHIPSSPREAD ) % CHIPSSPREAD;
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return qso;
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}
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// This IRQ is called periodically to fill the output buffer that is shifted to SPI
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void DMA1_Channel3_IRQHandler( void ) __attribute__((interrupt)) __attribute__((section(".srodata")));
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void DMA1_Channel3_IRQHandler( void )
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{
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//GPIOD->BSHR = 1; // Turn on GPIOD0 for profiling
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// Backup flags.
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volatile int intfr = DMA1->INTFR;
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do
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{
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// Clear all possible flags.
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DMA1->INTFCR = DMA1_IT_GL3;
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//int place = DMA1_Channel3->CNTR;
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// CNTR says that there are THIS MANY bytes left in the transfer.
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// So a high CNTR value indicates a very early place in the buffer.
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uint16_t * sb = 0;
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temp++;
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if( intfr & DMA1_IT_HT3 )
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{
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sb = sendbuff;
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}
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else if( intfr & DMA1_IT_TC3 )
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{
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sb = sendbuff + SENDBUFF_WORDS/2;
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}
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if( sb )
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{
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if( quadsetplace < 0 )
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{
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// Abort Send
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memset( sb, 0, SENDBUFF_WORDS*2/2 );
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DMA1_Channel3->CFGR &= ~DMA_CFGR1_EN;
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goto complete;
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}
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fxcycle += DMA_SIZE_WORDS;
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if( fxcycle == NUM_DMAS_PER_QUARTER_CHIRP*DMA_SIZE_WORDS )
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{
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fxcycle = 0;
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// Advance to next quarter word.
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quadsetplace++;
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if( quadsetplace > quadsetcount )
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{
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#ifdef TEST_TONE
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quadsetplace = 0;
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#else
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quadsetplace = -1;
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#endif
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memset( sb, 0, SENDBUFF_WORDS*2/2 );
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goto complete;
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}
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}
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int symbol = quadsets[quadsetplace]; // Actually 0...CHIRPLENGTHWORDS
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const uint16_t * tsb = 0;
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// Select down- or up-chirp.
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if( symbol < 0 )
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{
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int word = fxcycle - symbol - 1;
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if( word >= CHIRPLENGTH_WORDS ) word -= CHIRPLENGTH_WORDS;
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word++;
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tsb = (&chirpbuff[word+REVERSE_START_OFFSET_BYTES/4]);
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}
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else
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{
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int word = fxcycle + symbol;
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if( word >= CHIRPLENGTH_WORDS ) word -= CHIRPLENGTH_WORDS;
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tsb = (&chirpbuff[word]);
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}
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// I tried using the DMA to do the copy - but that didn't work for some reason.
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//while( DMA1_Channel2->CFGR & 1 );
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// DMA1_Channel2->CNTR = DMA_SIZE_WORDS/2;
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// DMA1_Channel2->MADDR = (uint32_t)tsb;
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// DMA1_Channel2->PADDR = (uint32_t)sb;
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// DMA1_Channel2->CFGR |= DMA_CFGR1_EN;
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int cpy = DMA_SIZE_WORDS/2;
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#ifdef TEST_TONE
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// Test tone
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memset( sb, 0xaa, cpy*2 );
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#else
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#if DMA_SIZE_WORDS_DIVISIBLE_BY_FOUR == 0
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#error need divisibiltiy by 2.
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#else
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//while( cpy-- ) { *(sb++) = wordo; }
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// Guarantee aligned access.
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uint32_t * sbw = (uint32_t*)(((uint32_t)sb)&~3);
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uint32_t * tsbw = (uint32_t*)(((uint32_t)tsb)&~3);
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//while( cpy-- ) { *(sbw++) = *(tsbw++); }
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// Align the data copy if needed
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if( cpy & 1 )
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{
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*(sbw++) = *(tsbw++);
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}
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cpy /= 2; // Doubled up per loop
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asm volatile("\
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1:\
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c.lw a3, 0(%[from])\n\
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c.lw a4, 4(%[from])\n\
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c.addi %[from], 8\n\
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c.addi %[cpy], -1\n\
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c.sw a3, 0(%[to])\n\
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c.sw a4, 4(%[to])\n\
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c.addi %[to], 8\n\
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c.bnez %[cpy], 1b\n\
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" : [cpy]"+r"(cpy), [from]"+r"(tsbw), [to]"+r"(sbw) : : "a3", "a4", "memory");
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#endif
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#endif
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}
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complete:
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intfr = DMA1->INTFR;
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} while( intfr );
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//GPIOD->BSHR = 1<<16; // Turn off GPIOD0 for profiling
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}
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#endif
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void LoopFunction() __attribute__((section(".srodata")));
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void LoopFunction()
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{
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uint8_t * start = (uint8_t*)DMA1_Channel2->MADDR;
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uint8_t * end = (uint8_t*)((uint32_t)DMA1_Channel2->MADDR + SENDBUFF_WORDS);
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uint8_t * here = start+ 8;
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uint32_t targ = 2000;
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uint32_t running = 0;
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uint8_t * tail = end - DMA1_Channel2->CNTR;
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uint32_t * cntr = DMA1_Channel2->CNTR;
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uint32_t temp = 0;
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uint32_t temp2 = 0;
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asm volatile("\n\
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li %[targ], 2000\n\
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genloop:\n\
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lw %[temp], 0(%[cntr])\n\
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sub %[tail], %[end], %[temp]\n\
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beq %[here], %[tail], genloop\n\
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innerloop:\
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li %[temp], 17\n\
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blt %[running], %[targ], noskip\n\
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li %[temp], 18\n\
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sub %[running], %[running], %[targ]\n\
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noskip:\n\
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sb %[temp], 0(%[here])\n\
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addi %[here], %[here], 1\n\
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bne %[here], %[end], skipreset\n\
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add %[here], x0, %[start]\n\
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skipreset:\n\
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bne %[here], %[tail], innerloop\n\
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j genloop\n\
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" : [here]"+r"(here) :
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[start]"r"(start),
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[end]"r"(end),
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[targ]"r"(targ),
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[running]"r"(running),
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[tail]"r"(tail),
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[cntr]"r"(cntr),
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[temp]"r"(temp),
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[temp2]"r"(temp2) );
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/*
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while(1)
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{
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int targ_f = 2000; //(frameno & 511)*9 + 1700;
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int run_f = 0;
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uint8_t * tail = end - DMA1_Channel2->CNTR;
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while( here != tail )
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{
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int setf = 17;
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if( run_f > targ_f )
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{
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setf = 18;
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run_f -= targ_f;
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}
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run_f += setf*32;
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*here = setf;
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here++;
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}
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*/
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/*
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for( j = 0; j < sizeof( sendbuff ); j++ )
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{
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int setf = 10;
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if( run_f > targ_f )
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{
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setf = 9;
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run_f -= targ_f;
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}
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run_f += setf*32;
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sendbuff[j] = setf;
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}
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*/
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}
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void LoopFunction2() __attribute__((aligned(256))) __attribute__((section(".srodata"))) __attribute__ ((noinline));
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__attribute__((section(".sdata"))) __attribute__((aligned(256))) const uint32_t tablef[] = {
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0x09090909,
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0x0909090a,
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0x090a090a,
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0x0a0a0a09,
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0x0a0a0a0a,
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0x0a0a0a0b,
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0x0a0b0a0b,
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0x0b0b0b0a,
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0x0b0b0b0b,
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0x0b0b0b0c,
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0x0b0c0b0c,
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0x0c0c0c0b,
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0x0c0c0c0c,
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0x0c0c0c0d,
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0x0c0d0c0d,
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0x0d0d0d0c,
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0x0d0d0d0d,
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};
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void LoopFunction2()
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{
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uint32_t * start = (uint8_t*)DMA1_Channel2->MADDR;
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uint32_t * end = (uint8_t*)((uint32_t)DMA1_Channel2->MADDR + SENDBUFF_WORDS);
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uint32_t * here = start;
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int run_f = 0;
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volatile uint32_t * cntrptr = &DMA1_Channel2->CNTR;
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while(1)
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{
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//uint32_t * tail = 0xfffffffc & (uintptr_t)(((uint8_t*)end) - *cntrptr);
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//if( tail == end ) tail--;
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uint32_t * tail = ((SENDBUFF_WORDS-1) & (0xfffffffc)) & (uintptr_t)(((uint8_t*)start) + SENDBUFF_WORDS - *cntrptr);
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while( here != tail )
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{
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uint32_t cp = ((SysTick->CNT>>14)&0xfff)+0x4000;
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*(here++) = tablef[run_f>>12];
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run_f &= 4095;
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run_f += cp;
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if( here == end )
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here = start;
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}
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}
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}
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int main()
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{
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SystemInit();
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funGpioInitAll();
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// Set a wait state (1 = normal <= 48MHz)
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FLASH->ACTLR = 1;
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// MCO for testing.
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// funPinMode( PA8, GPIO_CFGLR_OUT_50Mhz_AF_PP ); RCC->CFGR0 |= RCC_CFGR0_MCO_PLL;
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// printf( "Switching to HSE\n" );
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Delay_Ms( 10 );
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// Disable clock security system.
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RCC->CTLR &= ~RCC_CSSON;
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// Enable external crystal
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RCC->CTLR |= RCC_HSEON;
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// XXX NOTE: This is only used if you have a clock, not an oscillator.
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// RCC->CTLR |= RCC_HSEBYP;
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// Set System Clock Source to be 0.
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RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | 0;
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// Disable PLL
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RCC->CTLR &= ~RCC_PLLON;
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// Switch to HSE
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RCC->CFGR0 |= RCC_PLLSRC;
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// Enable PLL
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RCC->CTLR |= RCC_PLLON;
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// Wait for HSE to become ready.
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while( !( RCC->CTLR & RCC_HSERDY) );
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while( !( RCC->CTLR & RCC_PLLRDY) );
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RCC->CFGR0 |= RCC_SW_1; // Switch system clock to PLL
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// printf( "HSE Switched\n" );
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Delay_Ms( 10 );
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RCC->CTLR &= ~RCC_HSION;
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Delay_Ms( 10 );
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//printf( "HSI Off [%08lx %08lx]\n", RCC->CTLR, RCC->CFGR0 ); HSI Off [03035180 0001000a]
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC |
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RCC_APB2Periph_TIM1;
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RCC->AHBPCENR |= RCC_AHBPeriph_DMA1;
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funPinMode( PC3, GPIO_CFGLR_OUT_50Mhz_AF_PP ); // T1C3 on PC3
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RCC->APB2PRSTR |= RCC_APB2Periph_TIM1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1;
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// Prescaler
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TIM1->PSC = 0x0000;
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// Auto Reload - sets period
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TIM1->ATRLR = 20;
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// Reload immediately
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TIM1->SWEVGR |= TIM_UG;
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// Enable CH1N output, positive pol
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TIM1->CCER |= TIM_CC3E;
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TIM1->CCER |= TIM_CC1E;
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// Compare 3 = for output
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TIM1->CHCTLR2 =
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TIM_OC3M_0 | TIM_OC3M_1;
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// Compare 1 = for triggering
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TIM1->CHCTLR1 = TIM_OC1M_2 | TIM_OC1M_1;
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// Set the Capture Compare Register value to 50% initially
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TIM1->CH3CVR = 4;
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TIM1->CH1CVR = 0; // This triggers DMA.
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// Enable TIM1 outputs
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TIM1->BDTR |= TIM_MOE;
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// Enable TIM1
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TIM1->CTLR1 |= TIM_CEN;
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TIM1->DMAINTENR = TIM_TDE | TIM_COMDE | TIM_CC1DE | TIM_UDE;
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//DMA1_Channel3 is for SPI1TX
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DMA1_Channel2->PADDR = (uint32_t)&TIM1->ATRLR;
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DMA1_Channel2->MADDR = (uint32_t)sendbuff;
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DMA1_Channel2->CNTR = 0;// sizeof( bufferset )/2; // Number of unique copies. (Don't start, yet!)
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DMA1_Channel2->CFGR =
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DMA_M2M_Disable |
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DMA_Priority_VeryHigh |
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DMA_PeripheralDataSize_HalfWord |
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DMA_MemoryDataSize_Byte |
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DMA_MemoryInc_Enable |
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DMA_Mode_Circular | // OR DMA_Mode_Circular or DMA_Mode_Normal
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DMA_DIR_PeripheralDST |
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0;
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//DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts.
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// NVIC_EnableIRQ( DMA1_Channel3_IRQn );
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int j;
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for( j = 0; j < sizeof( sendbuff ); j++ )
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{
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sendbuff[j] = 12;
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}
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// Enter critical section.
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DMA1_Channel2->MADDR = (uint32_t)sendbuff;
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DMA1_Channel2->CNTR = SENDBUFF_WORDS; // Number of unique uint16_t entries.
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DMA1_Channel2->CFGR |= DMA_CFGR1_EN;
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int frameno = 0;
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// LoopFunction();
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LoopFunction2();
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#if 0
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uint32_t frame = 0;
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while(1)
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{
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Delay_Ms( 1000 );
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#ifdef LORAWAN
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// Optionally generate a LoRaWAN Packet.
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const static uint8_t raw_pl[4] = { 0xaa, 0xaa, 0xaa, 0xaa, };
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// Just some random data.
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static uint8_t raw_payload_with_b0[MAX_BYTES+8] = { 0 };
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uint8_t * payload_in = raw_payload_with_b0 + 16;
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int payload_in_size;
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// Be sure to provide your appropriate keys and address here.
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static const uint8_t payload_key[AES_BLOCKLEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; // AppSKey Big Endian
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static const uint8_t network_skey[AES_BLOCKLEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; // NwkSKey Big Endian
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static const uint8_t devaddress[4] = { 0x00, 0x00, 0x00, 0x00 }; // Device address Little Endian LSB (Written backwards from Device address default view)
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payload_in_size = GenerateLoRaWANPacket( raw_payload_with_b0, raw_pl, sizeof(raw_pl), payload_key, network_skey, devaddress, frame );
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#else
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uint8_t payload_in[15] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff };
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int payload_in_size = 15;
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#endif
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lora_symbols_count = 0;
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int r = CreateMessageFromPayload( lora_symbols, &lora_symbols_count, MAX_SYMBOLS, SF_NUMBER, 4, payload_in, payload_in_size );
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if( r < 0 )
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{
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printf( "Failed to generate message (%d)\n", r );
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// Failed
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continue;
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}
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frame++;
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int j;
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quadsetcount = 0;
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int16_t * qso = quadsets;
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for( j = 0; j < PREAMBLE_CHIRPS; j++ )
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{
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qso = AddChirp( qso, 0, 0 );
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}
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uint8_t syncword = 0x43;
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#if SF_NUMBER == 6
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#define CODEWORD_SHIFT 2
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#else
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#define CODEWORD_SHIFT 3
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#endif
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if( CODEWORD_LENGTH > 0 )
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qso = AddChirp( qso, ( ( syncword & 0xf ) << CODEWORD_SHIFT ), 0 );
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if( CODEWORD_LENGTH > 1 )
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qso = AddChirp( qso, ( ( ( syncword & 0xf0 ) >> 4 ) << CODEWORD_SHIFT ), 0);
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*(qso++) = -(CHIPSSPREAD * 0 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 1 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 2 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 3 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 0 / 4 )-1;
|
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*(qso++) = -(CHIPSSPREAD * 1 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 2 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 3 / 4 )-1;
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*(qso++) = -(CHIPSSPREAD * 0 / 4 )-1;
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if( SF_NUMBER <= 6 )
|
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{
|
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// Two additional upchirps with SF6 https://github.com/tapparelj/gr-lora_sdr/issues/74#issuecomment-1891569580
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for( j = 0; j < 2; j++ )
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qso = AddChirp( qso, 0, 0 );
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}
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|
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for( j = 0; j < lora_symbols_count; j++ )
|
|
{
|
|
int ofs = lora_symbols[j];
|
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qso = AddChirp( qso, ofs, 0 );
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}
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|
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runningcount_bits = 0;
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|
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// This tells the interrupt we have data.
|
|
quadsetcount = qso - quadsets + 0;
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printf( "- %d -- %d [%d] %d; %d\n", (int)temp, (int)lora_symbols_count, (int)quadsetcount, CHIPSSPREAD/4, sendbuff[0] );
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quadsetplace = 0;
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|
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DMA1_Channel3->CFGR |= DMA_CFGR1_EN;
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|
|
while( quadsetplace >= 0 );
|
|
}
|
|
#endif
|
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}
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