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https://github.com/cnlohr/lolra.git
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cnlohr
277 lines
7.6 KiB
C
277 lines
7.6 KiB
C
/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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// NOT LORA!!! -- but experimenting with the possibility of rx.
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// SETUP INSTRUCTIONS:
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// (1) `make` in the optionbytes folder to configure `RESET` correctly.
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// (2) Create a tone (if using the funprog, ../ch32v003fun/minichlink/minichlink -X ECLK 1:235:189:9:3 for 27.48387097MHz
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// (2) or, for 24.387096762MHz - ../ch32v003fun/minichlink/minichlink -X ECLK 1:150:49:8:3
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#include "ch32v003fun.h"
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#include <stdio.h>
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/* General note:
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Max speed was found to be:
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ADCclk = RCC / 2
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SAMPTR2 = 0 (3 cycles)
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PWM period = 27 (48/28 = 1.714MHz)
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If you go a little slower...
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ADCclk = RCC / 2
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SAMPTR2 = 1 (9 cycles)
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PWM period = 39 (48/40 = 1.2MHz)
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Perform Quadrature Decoding
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I = + + - -
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Q = + - - +
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We want the target waveform to be exactly n * Fs - fs / 4 = FBrd
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for a natural value of n.
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27 / (n-1/4) = Fs
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Oddly enough, after creating a table with various values of N and
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possible divisors, a PERFECT divisor works out to the "max speed" listed above (1.714MHz)
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but that makes me scared at this juncture. What if we intentionally just target 1.5MHz?
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1.5 = freq / (n-1/4)
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arbitrarily select n to be 17 (for the 17th harmonic)
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TODO: Is it supposed to be n-1/4 or n+1/4 or does it not matter?
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We are going to target 1.548387097MHz. (PPWM eriod = 30), Divisor = 31
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^^ /4 *64 = 24.7741935
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^^ /4 *63 = 24.387096762
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*/
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#define PWM_PERIOD 30
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#define ADC_BUFFSIZE 256
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volatile uint16_t adc_buffer[ADC_BUFFSIZE];
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void SetupADC()
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{
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// PD4 is analog input chl 7
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GPIOD->CFGLR &= ~(0xf<<(4*4)); // CNF = 00: Analog, MODE = 00: Input
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// Reset the ADC to init all regs
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RCC->APB2PRSTR |= RCC_APB2Periph_ADC1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1;
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// ADCCLK = 12 MHz => RCC_ADCPRE divide by 4
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RCC->CFGR0 &= ~RCC_ADCPRE; // Clear out the bis in case they were set
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RCC->CFGR0 |= RCC_ADCPRE_DIV2; // Fastest possible (divide-by-2) NOTE: This is OUTSIDE the specified value in the datasheet.
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// Set up single conversion on chl 7
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ADC1->RSQR1 = 0;
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ADC1->RSQR2 = 0;
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ADC1->RSQR3 = 7; // 0-9 for 8 ext inputs and two internals
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// Not using injection group.
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// Sampling time for channels. Careful: This has PID tuning implications.
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// Note that with 3 and 3,the full loop (and injection) runs at 138kHz.
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ADC1->SAMPTR2 = (0<<(3*7));
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// Turn on ADC and set rule group to sw trig
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// 0 = Use TRGO event for Timer 1 to fire ADC rule.
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ADC1->CTLR2 = ADC_ADON | ADC_EXTTRIG | ADC_DMA;
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// Reset calibration
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ADC1->CTLR2 |= ADC_RSTCAL;
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while(ADC1->CTLR2 & ADC_RSTCAL);
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// Calibrate ADC
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ADC1->CTLR2 |= ADC_CAL;
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while(ADC1->CTLR2 & ADC_CAL);
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// ADC_SCAN: Allow scanning.
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ADC1->CTLR1 = ADC_SCAN;
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// Turn on DMA
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RCC->AHBPCENR |= RCC_AHBPeriph_DMA1;
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//DMA1_Channel1 is for ADC
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DMA1_Channel1->PADDR = (uint32_t)&ADC1->RDATAR;
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DMA1_Channel1->MADDR = (uint32_t)adc_buffer;
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DMA1_Channel1->CNTR = ADC_BUFFSIZE;
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DMA1_Channel1->CFGR =
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DMA_M2M_Disable |
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DMA_Priority_VeryHigh |
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DMA_MemoryDataSize_HalfWord |
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DMA_PeripheralDataSize_HalfWord |
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DMA_MemoryInc_Enable |
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DMA_Mode_Circular |
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DMA_DIR_PeripheralSRC;
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// Turn on DMA channel 1
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DMA1_Channel1->CFGR |= DMA_CFGR1_EN;
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// Enable continuous conversion and DMA
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//ADC1->CTLR2 |= ADC_DMA | ADC_EXTSEL; //ADC_CONT
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// start conversion
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ADC1->CTLR2 |= ADC_SWSTART;
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}
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static void SetupTimer1()
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{
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// Enable Timer 1
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RCC->APB2PRSTR |= RCC_APB2Periph_TIM1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1;
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TIM1->PSC = 0x0000; // Prescalar to 0x0000 (so, 48MHz base clock)
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TIM1->ATRLR = PWM_PERIOD;
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// NOT USED
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//TIM1->CCER = TIM_CC2E | TIM_CC2NP; // CH2 is control for FET.
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//TIM1->CHCTLR1 = TIM_OC2M_2 | TIM_OC2M_1;
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TIM1->CH2CVR = 0; // Actual duty cycle (Off to begin with)
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// Setup TRGO for ADC. This makes is to the ADC will trigger on timer
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// reset, so we trigger at the same position every time relative to the
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// FET turning on.
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TIM1->CTLR2 = TIM_MMS_1;
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// Enable TIM1 outputs
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TIM1->BDTR = TIM_MOE;
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TIM1->CTLR1 = TIM_CEN;
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}
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void InnerLoop() __attribute__((noreturn));
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void InnerLoop()
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{
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int i = 0;
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int q = 0;
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int tpl = 0;
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// Timer goes backwards when we are moving forwards.
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volatile uint16_t * adc_buffer_end = 0;
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volatile uint16_t * adc_buffer_top = adc_buffer + ADC_BUFFSIZE;
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volatile uint16_t * adc = adc_buffer;
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int frcnt = 0;
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int tstart = 0;
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while( 1 )
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{
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tpl = ADC_BUFFSIZE - DMA1_Channel1->CNTR; // Warning, sometimes this is == to the base, or == 0 (i.e. might be 256, if top is 255)
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if( tpl == ADC_BUFFSIZE ) tpl = 0;
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adc_buffer_end = adc_buffer + ( ( tpl / 4) * 4 );
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while( adc != adc_buffer_end )
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{
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int32_t t = adc[0];
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i += t; q += t;
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t = adc[1];
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i -= t; q += t;
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t = adc[2];
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i -= t; q -= t;
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t = adc[3];
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i += t; q -= t;
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adc += 4;
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frcnt += 4;
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if( adc == adc_buffer_top ) adc = adc_buffer;
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}
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if( frcnt > 1000000 )
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{
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printf( "I: %6d Q: %6d [%d %d %d %d] / %d\n", i ,q, adc_buffer[0], adc_buffer[1], adc_buffer[2], adc_buffer[3], SysTick->CNT - tstart );
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frcnt = 0;
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i = 0;
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q = 0;
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tstart = SysTick->CNT;
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}
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/*
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Delay_Us( 100 );
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int end = DMA1_Channel1->CNTR;
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int v0 = adc_buffer[0];
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int v1 = adc_buffer[1];
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int v2 = adc_buffer[2];
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int v3 = adc_buffer[3];
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printf( "%d %d %d %d %d\n", (uint8_t)(start-end), v0, v1, v2, v3 );
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*/
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}
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}
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int main()
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{
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// REQUIRES External 24MHz oscillator
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printf( "Initializing\n" );
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SystemInit();
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printf( "System On\n" );
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// Enable Peripherals
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC |
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RCC_APB2Periph_GPIOA | RCC_APB2Periph_TIM1 | RCC_APB2Periph_ADC1 |
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RCC_APB2Periph_AFIO;
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RCC->APB1PCENR = RCC_APB1Periph_TIM2;
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SetupADC();
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printf( "ADC Setup\n" );
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SetupTimer1();
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printf( "Timer 1 setup\n" );
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InnerLoop();
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}
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