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https://github.com/cnlohr/lolra.git
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cnlohr
358 lines
11 KiB
C
358 lines
11 KiB
C
/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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#include <stdio.h>
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#include <string.h>
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#include "esp_system.h"
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#include "hal/gpio_types.h"
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#include "esp_log.h"
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#include "soc/efuse_reg.h"
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#include "soc/soc.h"
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#include "soc/system_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dedic_gpio_reg.h"
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#include "image.h"
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// Funtenna will output on GPIO1 and 14. Otherwise it will be 17 and 18
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//#define FUNTENNA
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int global_i = 100;
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static inline uint32_t getCycleCount()
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{
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uint32_t ccount;
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asm volatile("rsr %0,ccount":"=a" (ccount));
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return ccount;
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}
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#define IO_MUX_REG(x) XIO_MUX_REG(x)
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#define XIO_MUX_REG(x) IO_MUX_GPIO##x##_REG
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#define GPIO_NUM(x) XGPIO_NUM(x)
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#define XGPIO_NUM(x) GPIO_NUM_##x
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#ifdef FUNTENNA
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#define RF1_PIN 1
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#define RF2_PIN 14
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#else
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#define RF1_PIN 17
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#define RF2_PIN 18
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#endif
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#include "hal/gpio_types.h"
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#include "driver/gpio.h"
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#include "rom/gpio.h"
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#include "soc/i2s_reg.h"
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#include "soc/periph_defs.h"
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#include "rom/lldesc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc.h"
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#include "soc/regi2c_apll.h"
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//#include "components/hal/esp32s2/include/hal/regi2c_ctrl_ll.h
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#include "hal/regi2c_ctrl_ll.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "hal/clk_tree_ll.h"
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#include "siggen.h"
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#define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG)
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#define I2C_RTC_CLK_GATE_EN (BIT(18))
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#define I2C_RTC_CLK_GATE_EN_M (BIT(18))
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#define I2C_RTC_CLK_GATE_EN_V 0x1
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#define I2C_RTC_CLK_GATE_EN_S 18
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#define I2C_RTC_CONFIG0 0x6000e048
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#define I2C_RTC_MAGIC_CTRL 0x00001FFF
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#define I2C_RTC_MAGIC_CTRL_M ((I2C_RTC_MAGIC_CTRL_V)<<(I2C_RTC_MAGIC_CTRL_S))
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#define I2C_RTC_MAGIC_CTRL_V 0x1FFF
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#define I2C_RTC_MAGIC_CTRL_S 4
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#define I2C_RTC_CONFIG1 0x6000e044
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#define I2C_RTC_BOD_MASK (BIT(22))
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#define I2C_RTC_BOD_MASK_M (BIT(22))
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#define I2C_RTC_BOD_MASK_V 0x1
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#define I2C_RTC_BOD_MASK_S 22
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#define I2C_RTC_SAR_MASK (BIT(18))
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#define I2C_RTC_SAR_MASK_M (BIT(18))
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#define I2C_RTC_SAR_MASK_V 0x1
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#define I2C_RTC_SAR_MASK_S 18
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#define I2C_RTC_BBPLL_MASK (BIT(17))
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#define I2C_RTC_BBPLL_MASK_M (BIT(17))
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#define I2C_RTC_BBPLL_MASK_V 0x1
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#define I2C_RTC_BBPLL_MASK_S 17
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#define I2C_RTC_APLL_MASK (BIT(14))
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#define I2C_RTC_APLL_MASK_M (BIT(14))
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#define I2C_RTC_APLL_MASK_V 0x1
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#define I2C_RTC_APLL_MASK_S 14
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#define I2C_RTC_ALL_MASK 0x00007FFF
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#define I2C_RTC_ALL_MASK_M ((I2C_RTC_ALL_MASK_V)<<(I2C_RTC_ALL_MASK_S))
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#define I2C_RTC_ALL_MASK_V 0x7FFF
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#define I2C_RTC_ALL_MASK_S 8
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#define I2C_RTC_CONFIG2 0x6000e000
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#define I2C_RTC_BUSY (BIT(25))
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#define I2C_RTC_BUSY_M (BIT(25))
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#define I2C_RTC_BUSY_V 0x1
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#define I2C_RTC_BUSY_S 25
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#define I2C_RTC_WR_CNTL (BIT(24))
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#define I2C_RTC_WR_CNTL_M (BIT(24))
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#define I2C_RTC_WR_CNTL_V 0x1
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#define I2C_RTC_WR_CNTL_S 24
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#define I2C_RTC_DATA 0x000000FF
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#define I2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
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#define I2C_RTC_DATA_V 0xFF
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#define I2C_RTC_DATA_S 16
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#define I2C_RTC_ADDR 0x000000FF
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#define I2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
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#define I2C_RTC_ADDR_V 0xFF
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#define I2C_RTC_ADDR_S 8
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#define I2C_RTC_SLAVE_ID 0x000000FF
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#define I2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
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#define I2C_RTC_SLAVE_ID_V 0xFF
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#define I2C_RTC_SLAVE_ID_S 0
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#define I2C_RTC_MAGIC_DEFAULT (0x1c40)
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#define I2C_BOD 0x61
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#define I2C_BBPLL 0x66
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#define I2C_SAR_ADC 0X69
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#define I2C_APLL 0X6D
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int lastend = 0;
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// Configures APLL = 480 / 4 = 120
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// 40 * (SDM2 + SDM1/(2^8) + SDM0/(2^16) + 4) / ( 2 * (ODIV+2) );
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// Datasheet recommends that numerator does not exceed 500MHz.
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void IRAM_ATTR local_rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
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{
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REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
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REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
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if (enable) {
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
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REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, CLK_LL_APLL_SDM_STOP_VAL_1);
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REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, CLK_LL_APLL_SDM_STOP_VAL_2_REV1);
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div );
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}
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// Settings determined experimentally.
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OC_TSCHGP, 0 ); // 0 or 1
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_EN_FAST_CAL, 1 ); // 0 or 1
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OC_DHREF_SEL, 0 ); // 0..3
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OC_DLREF_SEL, 0 ); // 0..3
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_SDM_DITHER, 1 ); // 0 or 1
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REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OC_DVDD, 25 ); // 0 .. 31
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}
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void IRAM_ATTR regi2c_write_reg_raw_local(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
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{
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uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
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| ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
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| ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
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| (((uint32_t)data & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
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while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
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REG_WRITE(I2C_RTC_CONFIG2, temp);
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}
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void apll_quick_update( uint32_t sdm )
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{
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uint8_t sdm2 = sdm>>16;
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uint8_t sdm1 = (sdm>>8)&0xff;
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uint8_t sdm0 = (sdm>>0)&0xff;
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static int last_sdm_0 = -1;
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static int last_sdm_1 = -1;
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static int last_sdm_2 = -1;
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if( sdm2 != last_sdm_2 )
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regi2c_write_reg_raw_local(I2C_APLL, I2C_APLL_HOSTID, I2C_APLL_DSDM2, sdm2);
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if( sdm0 != last_sdm_0 )
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regi2c_write_reg_raw_local(I2C_APLL, I2C_APLL_HOSTID, I2C_APLL_DSDM0, sdm0);
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if( sdm1 != last_sdm_1 )
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regi2c_write_reg_raw_local(I2C_APLL, I2C_APLL_HOSTID, I2C_APLL_DSDM1, sdm1);
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last_sdm_2 = sdm2;
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last_sdm_1 = sdm1;
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last_sdm_0 = sdm0;
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}
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void sandbox_main()
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{
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printf( "sandbox_main()\n" );
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DPORT_SET_PERI_REG_MASK( DPORT_CPU_PERI_CLK_EN_REG, DPORT_CLK_EN_DEDICATED_GPIO );
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DPORT_CLEAR_PERI_REG_MASK( DPORT_CPU_PERI_RST_EN_REG, DPORT_RST_EN_DEDICATED_GPIO);
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// Setup GPIO39 to be the PRO ALONE output (For LEDs)
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REG_WRITE( GPIO_OUT1_W1TC_REG, 1<<(39-32) );
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REG_WRITE( GPIO_ENABLE1_W1TS_REG, 1<<(39-32) );
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REG_WRITE( IO_MUX_GPIO39_REG, 2<<FUN_DRV_S );
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REG_WRITE( GPIO_FUNC39_OUT_SEL_CFG_REG, PRO_ALONEGPIO_OUT0_IDX );
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REG_WRITE( DEDIC_GPIO_OUT_CPU_REG, 0x01 ); // Enable CPU instruction output
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// Output clock on P2.
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// Maximize the drive strength.
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gpio_set_drive_capability( GPIO_NUM(RF1_PIN), GPIO_DRIVE_CAP_3 );
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gpio_set_drive_capability( GPIO_NUM(RF2_PIN), GPIO_DRIVE_CAP_3 );
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// Use the IO matrix to create the inverse of TX on pin 17.
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gpio_matrix_out( GPIO_NUM(RF1_PIN), CLK_I2S_MUX_IDX, 1, 0 );
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gpio_matrix_out( GPIO_NUM(RF2_PIN), CLK_I2S_MUX_IDX, 0, 0 );
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periph_module_enable(PERIPH_I2S0_MODULE);
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int use_apll = 1;
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int sdm0 = 100;
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int sdm1 = 230;
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int sdm2 = 8;
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int odiv = 0;
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local_rtc_clk_apll_enable( use_apll, sdm0, sdm1, sdm2, odiv );
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if( use_apll )
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{
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WRITE_PERI_REG( I2S_CLKM_CONF_REG(0), (1<<I2S_CLK_SEL_S) | (1<<I2S_CLK_EN_S) | (0<<I2S_CLKM_DIV_A_S) | (0<<I2S_CLKM_DIV_B_S) | (1<<I2S_CLKM_DIV_NUM_S) );
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}
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else
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{
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// fI2S = fCLK / ( N + B/A )
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// DIV_NUM = N
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// Note I2S_CLKM_DIV_NUM minimum = 2 by datasheet. Less than that and it will ignoreeee you.
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WRITE_PERI_REG( I2S_CLKM_CONF_REG(0), (2<<I2S_CLK_SEL_S) | (1<<I2S_CLK_EN_S) | (0<<I2S_CLKM_DIV_A_S) | (0<<I2S_CLKM_DIV_B_S) | (1<<I2S_CLKM_DIV_NUM_S) ); // Minimum reduction, 2:1
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}
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gpio_matrix_out( GPIO_NUM(RF1_PIN), CLK_I2S_MUX_IDX, 1, 0 );
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gpio_matrix_out( GPIO_NUM(RF2_PIN), CLK_I2S_MUX_IDX, 0, 0 );
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// SigSetupTest( );
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lastend = getCycleCount();
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}
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#define DisableISR() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
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#define EnableISR() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
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uint32_t frame = 0;
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void sandbox_tick()
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{
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int iterations = 0;
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for( iterations = 0; iterations < 10000; iterations++ )
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{
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uint32_t start = getCycleCount() & 0x7fffffff;
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int cell = start / (uint32_t)(( 0x7fffffff / (IMAGEOH*IMAGEOPL) ));
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// Determine what value we should actually be outputting to the APLL.
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// By blasting through our image table.
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int value = imageout[IMAGEOH*IMAGEOPL - 1 - cell];
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uint32_t base = 648985;
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if( value == 0 )
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{
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gpio_matrix_out( GPIO_NUM(RF1_PIN), CLK_I2S_MUX_IDX, 1, 1 );
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gpio_matrix_out( GPIO_NUM(RF2_PIN), CLK_I2S_MUX_IDX, 0, 1 );
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}
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else
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{
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apll_quick_update( base + value*6 /* Controls width */ ); // (cell % 4000) );
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gpio_matrix_out( GPIO_NUM(RF1_PIN), CLK_I2S_MUX_IDX, 1, 0 );
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gpio_matrix_out( GPIO_NUM(RF2_PIN), CLK_I2S_MUX_IDX, 0, 0 );
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}
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}
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}
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struct SandboxStruct
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{
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void (*fnIdle)();
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};
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struct SandboxStruct sandbox_mode =
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{
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.fnIdle = sandbox_tick,
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};
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