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https://github.com/cnlohr/lolra.git
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add rx/tx test
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cnlohr
@@ -0,0 +1,13 @@
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all : flash
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TARGET:=ch32v003rx
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TARGET_MCU:=CH32V003
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CH32V003FUN:=../../ch32v003fun/ch32v003fun
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EXTRA_CFLAGS:=-Wno-unused-function -I../../lib
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include $(CH32V003FUN)/ch32v003fun.mk
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flash : cv_flash
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clean : cv_clean
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@@ -0,0 +1,208 @@
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/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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#include "ch32v003fun.h"
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#include <stdio.h>
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#define ADC_NUMCHLS 1
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#define DMA_SIZE 512
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#define ADC_PIN PC4
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#define ADCNO 2
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#define LEDPIN PD6
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uint32_t dmadata[DMA_SIZE/2] __attribute__((aligned(64)));
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int32_t lastintenR, lastintenI;
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uint32_t wordouts;
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void DMA1_Channel1_IRQHandler( void ) __attribute__((interrupt));
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void DMA1_Channel1_IRQHandler( void )
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{
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DMA1_Channel1->CFGR |= DMA_CFGR1_EN;
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// Clear all possible flags.
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DMA1->INTFCR = DMA1_IT_GL1;
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uint32_t * head = dmadata;
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uint32_t * end = dmadata + DMA_SIZE/2;
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static uint32_t * here = dmadata;
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static uint32_t thisintenR;
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static uint32_t thisintenI;
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// We have a pointer to the next data we want to analyize.
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// We have a pointer to where the tail of the new data is.
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// We want to process data from where we are to where the
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// data ends.
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// So, we set and end point, which could be either the end
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// of where the data is or the end of the array with the
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// data.
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// Then we plow through the data until we get to one of those
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// two. And we either reset the pointer to the beginning of
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// the array, OR, we stop because we ran out of data.
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do
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{
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uint32_t cnt = DMA1_Channel1->CNTR;
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if( cnt == 0 ) cnt = 1;
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uint32_t tail_offset = DMA_SIZE - cnt;
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uint32_t * tail = dmadata + tail_offset/2; // Tuncate down to quads if a pair has not been fully written.
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uint32_t * stopat = (here < tail) ? tail : end;
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if( here == tail ) break;
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do
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{
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int32_t vA = *(here++);
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int32_t vB = *(here++);
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thisintenR += ((int16_t)vA) - (vB >> 16);
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thisintenI += ((int16_t)vB) - (vA >> 16);
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} while( here != stopat );
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if( here == end )
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{
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lastintenR = thisintenR; // Fixup (because when we were subtracting, it should be -1)
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lastintenI = thisintenI; // Fixup (because when we were subtracting, it should be -1)
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thisintenR = 0;
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thisintenI = 0;
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here = head;
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wordouts++;
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}
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if( here == tail ) break;
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}
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while( 1 );
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}
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int main()
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{
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SystemInit();
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Delay_Ms( 100 );
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funGpioInitAll();
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RCC->APB1PCENR |= RCC_APB1Periph_TIM2;
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RCC->APB2PCENR |= RCC_APB2Periph_ADC1;
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// Reset the ADC to init all regs
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RCC->APB2PRSTR |= RCC_APB2Periph_ADC1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1;
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ADC1->RSQR1 = (1-1) << 20; // One channel.
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ADC1->RSQR2 = 0;
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ADC1->RSQR3 = (ADCNO<<(5*0));
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// set sampling time for chl 7, 4, 3, 2
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// 0:7 => 3/9/15/30/43/57/73/241 cycles
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ADC1->SAMPTR2 = (0<<(3*ADCNO));
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// turn on ADC
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ADC1->CTLR2 = ADC_ADON;
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// Reset calibration
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ADC1->CTLR2 = ADC_ADON | ADC_RSTCAL;
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while(ADC1->CTLR2 & ADC_RSTCAL);
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// Calibrate
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ADC1->CTLR2 = ADC_ADON | ADC_CAL;
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while(ADC1->CTLR2 & ADC_CAL);
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// Turn on DMA
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RCC->AHBPCENR |= RCC_AHBPeriph_DMA1;
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//DMA1_Channel1 is for ADC
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DMA1_Channel1->PADDR = (uint32_t)&ADC1->RDATAR;
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DMA1_Channel1->MADDR = (uint32_t)dmadata;
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DMA1_Channel1->CNTR = DMA_SIZE;
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DMA1_Channel1->CFGR =
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DMA_M2M_Disable |
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DMA_Priority_VeryHigh |
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DMA_MemoryDataSize_HalfWord |
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DMA_PeripheralDataSize_HalfWord |
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DMA_MemoryInc_Enable |
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DMA_Mode_Circular |
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DMA_DIR_PeripheralSRC |
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DMA_IT_TC | DMA_IT_HT; // Transmission Complete + Half Empty Interrupts.
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// NVIC_SetPriority( DMA1_Channel3_IRQn, 0<<4 ); //We don't need to tweak priority.
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NVIC_EnableIRQ( DMA1_Channel1_IRQn );
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DMA1_Channel1->CFGR |= DMA_CFGR1_EN; // Turn on DMA channel 1
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ADC1->CTLR1 |= ADC_SCAN; // enable scanning
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// Enable continuous conversion and DMA, selected by TIM2CC1
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ADC1->CTLR2 = ADC_ADON | ADC_DMA | ADC_EXTSEL_2 | ADC_EXTTRIG;
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// start conversion
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ADC1->CTLR2 |= ADC_SWSTART;
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// PD4 = T2C1
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funPinMode( LEDPIN, GPIO_CFGLR_OUT_50Mhz_PP );
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funPinMode( PD4, GPIO_CFGLR_OUT_50Mhz_AF_PP );
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funPinMode( ADC_PIN, GPIO_CFGLR_IN_ANALOG );
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// Reset TIM2 to init all regs
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RCC->APB1PRSTR |= RCC_APB1Periph_TIM2;
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RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2;
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TIM2->PSC = 0x0000; // Prescalar
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TIM2->ATRLR = 47; // TIM2 max before reset.
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TIM2->CHCTLR1 = TIM_OC1M_2 | TIM_OC1M_1 | TIM_OC1PE;
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TIM2->CTLR1 = TIM_ARPE;
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TIM2->CCER = TIM_CC1E | TIM_CC1P | TIM_CC1NP;
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TIM2->SWEVGR = TIM_UG;
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// Enable TIM2 (T2C1 = Trigger ADC)
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TIM2->CTLR1 |= TIM_CEN;
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TIM2->CH1CVR = 1;
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while(1)
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{
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printf( "%5d %5d %6d\n", (int)lastintenR, (int)lastintenI, (int)wordouts );
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}
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}
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@@ -0,0 +1,9 @@
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#ifndef _FUNCONFIG_H
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#define _FUNCONFIG_H
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#define FUNCONF_USE_DEBUGPRINTF 1
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#define FUNCONF_USE_UARTPRINTF 0
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#define FUNCONF_USE_HSE 1
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#endif
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