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https://github.com/cnlohr/lolra.git
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Add test fft
This commit is contained in:
cnlohr
@@ -0,0 +1,401 @@
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/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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// NOT LORA!!! -- but experimenting with the possibility of rx.
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// SETUP INSTRUCTIONS:
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// (1) `make` in the optionbytes folder to configure `RESET` correctly.
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// (2) Create a tone (if using the funprog, ../ch32v003fun/minichlink/minichlink -X ECLK 1:235:189:9:3 for 27.48387097MHz
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// (2) or, for 24.387096762MHz - ../ch32v003fun/minichlink/minichlink -X ECLK 1:150:49:8:3
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/* More notes
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* Minimum sample time with DMA = fCPU / 28 (5.14MHz)
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*/
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#include "ch32v003fun.h"
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#include <stdio.h>
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#define SH1107_128x128
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#include "ssd1306_i2c.h"
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#include "ssd1306.h"
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#define FIX_FFT_IMPLEMENTATION
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#include "fix_fft.h"
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/* General note:
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*/
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#define Q 128
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#define PWM_PERIOD (36-1) //For 27.0MHz -- It appears to be good for *244 in the table? WHY 26MHz???!?!!?
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#define ADC_BUFFSIZE 256
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volatile uint16_t adc_buffer[ADC_BUFFSIZE];
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void SetupADC()
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{
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// XXX TODO -look into PGA
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// XXX TODO - Look into tag-teaming the ADCs
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// PDA is analog input chl 7
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GPIOA->CFGLR &= ~(0xf<<(4*7)); // CNF = 00: Analog, MODE = 00: Input
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// ADC CLK is chained off of APB2.
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// Reset the ADC to init all regs
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RCC->APB2PRSTR |= RCC_APB2Periph_ADC1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_ADC1;
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// ADCCLK = 12 MHz => RCC_ADCPRE divide by 4
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RCC->CFGR0 &= ~RCC_ADCPRE; // Clear out the bis in case they were set
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RCC->CFGR0 |= RCC_ADCPRE_DIV2; // Fastest possible (divide-by-2) NOTE: This is OUTSIDE the specified value in the datasheet.
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// Set up single conversion on chl 7
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ADC1->RSQR1 = 0;
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ADC1->RSQR2 = 0;
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ADC1->RSQR3 = 7; // 0-9 for 8 ext inputs and two internals
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// Not using injection group.
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// Sampling time for channels. Careful: This has PID tuning implications.
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// Note that with 3 and 3,the full loop (and injection) runs at 138kHz.
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ADC1->SAMPTR2 = (0<<(3*7));
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// Turn on ADC and set rule group to sw trig
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// 0 = Use TRGO event for Timer 1 to fire ADC rule.
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ADC1->CTLR2 = ADC_ADON | ADC_EXTTRIG | ADC_DMA;
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// Reset calibration
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ADC1->CTLR2 |= ADC_RSTCAL;
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while(ADC1->CTLR2 & ADC_RSTCAL);
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// Calibrate ADC
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ADC1->CTLR2 |= ADC_CAL;
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while(ADC1->CTLR2 & ADC_CAL);
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// ADC_SCAN: Allow scanning.
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ADC1->CTLR1 = /*ADC_Pga_64 | */ADC_SCAN;
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// Turn on DMA
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RCC->AHBPCENR |= RCC_AHBPeriph_DMA1;
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//DMA1_Channel1 is for ADC
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DMA1_Channel1->PADDR = (uint32_t)&ADC1->RDATAR;
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DMA1_Channel1->MADDR = (uint32_t)adc_buffer;
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DMA1_Channel1->CNTR = ADC_BUFFSIZE;
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DMA1_Channel1->CFGR =
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DMA_M2M_Disable |
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DMA_Priority_VeryHigh |
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DMA_MemoryDataSize_HalfWord |
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DMA_PeripheralDataSize_HalfWord |
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DMA_MemoryInc_Enable |
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DMA_Mode_Circular |
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DMA_DIR_PeripheralSRC;
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// Turn on DMA channel 1
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DMA1_Channel1->CFGR |= DMA_CFGR1_EN;
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// Enable continuous conversion and DMA
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ADC1->CTLR2 |= ADC_DMA; // | ADC_CONT;
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// start conversion
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ADC1->CTLR2 |= ADC_SWSTART;// | ADC_CONT;
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}
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static void SetupTimer1()
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{
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// Enable Timer 1
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RCC->APB2PRSTR |= RCC_APB2Periph_TIM1;
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RCC->APB2PRSTR &= ~RCC_APB2Periph_TIM1;
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TIM1->PSC = 0; // Prescalar to 0x0000 (so, 48MHz base clock)
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TIM1->ATRLR = PWM_PERIOD;
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#ifdef PWM_OUTPUT
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// PA10 = T1CH3.
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GPIOA->CFGHR &= ~(0xf<<(4*2));
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GPIOA->CFGHR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*2);
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TIM1->CCER = TIM_CC3E | TIM_CC3P;
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TIM1->CHCTLR2 = TIM_OC3M_2 | TIM_OC3M_1;
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TIM1->CH3CVR = 5; // Actual duty cycle (Off to begin with)
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#endif
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TIM1->CCER = TIM_CC1E;
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TIM1->CHCTLR1 = TIM_OC1M_2 | TIM_OC1M_1;
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TIM1->CH1CVR = 1;
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// Setup TRGO to trigger for ADC (NOTE: Not on the 203! TIM1_TRGO is only connected to injection)
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//TIM1->CTLR2 = TIM_MMS_1;
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// Enable TIM1 outputs
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TIM1->BDTR = TIM_MOE;
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TIM1->CTLR1 = TIM_CEN;
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}
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void InnerLoop() __attribute__((noreturn));
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void InnerLoop()
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{
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int i = 0;
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int q = 0;
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int tpl = 0;
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// Timer goes backwards when we are moving forwards.
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volatile uint16_t * adc_buffer_end = 0;
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volatile uint16_t * adc_buffer_top = adc_buffer + ADC_BUFFSIZE;
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volatile uint16_t * adc = adc_buffer;
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int frcnt = 0;
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int tstart = 0;
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int16_t shadowbuff[Q+16];
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int shadowplace = 0;
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#define SHADOWSTORE(X) shadowbuff[frcnt+X] = t<<3;
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while( 1 )
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{
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tpl = ADC_BUFFSIZE - DMA1_Channel1->CNTR; // Warning, sometimes this is == to the base, or == 0 (i.e. might be 256, if top is 255)
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if( tpl == ADC_BUFFSIZE ) tpl = 0;
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adc_buffer_end = adc_buffer + ( ( tpl / 4) * 4 );
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//printf( "%3d %4d %d %04x\n", DMA1_Channel1->CNTR, TIM1->CNT, ADC1->RDATAR, ADC1->STATR );
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while( adc != adc_buffer_end )
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{
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int32_t t = adc[0]; SHADOWSTORE(0);
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i += t; q += t;
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t = adc[1]; SHADOWSTORE(1);
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i -= t; q += t;
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t = adc[2]; SHADOWSTORE(2);
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i -= t; q -= t;
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t = adc[3]; SHADOWSTORE(3);
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i += t; q -= t;
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adc += 4;
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frcnt += 4;
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if( adc == adc_buffer_top ) adc = adc_buffer;
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if( frcnt >= Q ) break;
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}
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if( frcnt >= Q )
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{
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#if 0
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#ifdef DUMPBUFF
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int j;
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for( j = 0; j < Q; j++ )
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printf( "%d,%d\n", j, shadowbuff[j] );
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#endif
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#ifdef QUADRATURE
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int ti = i>>3;
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int tq = q>>3;
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int is = (ti*ti + tq*tq)>>8;
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#else
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int is = i>>2;
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#endif
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int s = 1<<( ( 32 - __builtin_clz(is) )/2);
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s = (s + is/s)/2;
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#ifdef TIGHT_OUT
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printf( "%d\n", s );
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#elif defined( PWM_OUTPUT )
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int tv = (s>>PWM_OUTPUT) + (PWM_PERIOD/2);
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if( tv < 0 ) tv = 0;
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if( tv >= PWM_PERIOD ) tv = PWM_PERIOD-1;
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TIM1->CH3CVR = tv;
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#else
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printf( "%8d I:%7d Q:%7d [%d %d %d %d] / %d\n",s, i ,q, adc_buffer[0], adc_buffer[1], adc_buffer[2], adc_buffer[3], (int)(SysTick->CNT - tstart) );
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#endif
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//printf( "%d\n", s );
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#endif
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int k;
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int osb = shadowbuff[0];
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int16_t FSQ[Q] = { 0 };
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for( k = 0; k < 128; k++ )
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{
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ssd1306_drawPixel( k, ((shadowbuff[k]-osb)>>3)+32, 1 );
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}
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int r =
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//fix_fftr(shadowbuff, 7 /*1<<7 = 128 bins wide*/, 0);
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fix_fft(shadowbuff, FSQ, 7 /*1<<7 = 128 bins wide*/, 0);
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for( k = 0; k < 128; k++ )
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{
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/*
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int s = shadowbuff[k] * shadowbuff[k] + FSQ[k]*FSQ[k];
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//if( s == 0 ) continue;
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int x = 1<<( ( 32 - __builtin_clz(s) )/2);
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x = (x + i/x)/2;
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x = (x + i/x)/2; //Not really needed.
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*/
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// for real
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// int x = shadowbuff[(k>>1) | ((k&64)>>6)];
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// For faked imag
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int x = shadowbuff[ k ];
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x++;
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if( x < 0 ) x = 0;
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if( x > 127 ) x = 127;
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if( x != 0 )
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ssd1306_drawFastVLine( k, 127-x, x, 1 );
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if( k== 0 )
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{
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char cts[16];
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snprintf( cts, sizeof(cts), "%7d%5d", x, osb );
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ssd1306_drawstr( 0, 0, cts, 1 );
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}
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}
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memset( shadowbuff, 0, sizeof( shadowbuff ) );
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ssd1306_refresh();
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ssd1306_setbuf(0);
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frcnt = 0;
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i = 0;
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q = 0;
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tpl = ADC_BUFFSIZE - DMA1_Channel1->CNTR;
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adc = adc_buffer + ( ( tpl / 4) * 4 );
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tstart = SysTick->CNT;
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}
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/*
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Delay_Us( 100 );
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int end = DMA1_Channel1->CNTR;
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int v0 = adc_buffer[0];
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int v1 = adc_buffer[1];
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int v2 = adc_buffer[2];
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int v3 = adc_buffer[3];
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printf( "%d %d %d %d %d\n", (uint8_t)(start-end), v0, v1, v2, v3 );
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*/
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}
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}
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int main()
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{
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SystemInit();
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SysTick->CTLR = (1<<2) | 1; // HCLK
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Delay_Ms(100);
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printf( "System On\n" );
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// x18; 8MHz x 18 = 144 MHz
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RCC->CFGR0 &= ~RCC_PPRE2; // No divisor on APB1/2
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RCC->CFGR0 &= ~RCC_PPRE1;
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RCC->CFGR0 |= RCC_PLLMULL_0 | RCC_PLLMULL_1 | RCC_PLLMULL_2 | RCC_PLLMULL_3;
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Delay_Ms(50);
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// Disable HSI
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RCC->CTLR &= ~(RCC_HSION);
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// printf( "RCC: %08x\n", (RCC->CFGR0) );
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RCC->AHBPCENR |= 3; //DMA2EN | DMA1EN
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RCC->APB2PCENR |= RCC_APB2Periph_TIM1 | RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 | 0x07; // Enable all GPIO
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RCC->APB1PCENR |= RCC_APB1Periph_TIM2;
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SetupADC();
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printf( "Setting up OLED.\n" );
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ssd1306_i2c_setup();
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uint8_t ret = ssd1306_i2c_init();
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ssd1306_init();
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ssd1306_setbuf(0);
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#if 0
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int i = 0;
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int k = 0;
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int frame = 0;
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while( 1)
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{
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// ssd1306_drawLine( (frame)%128, (0)%128, (0)%128, (127-frame)%128, 1 );
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ssd1306_drawstr( frame%128, frame%128, "hello", 1 );
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ssd1306_refresh();
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ssd1306_setbuf(0);
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frame++;
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}
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while(1);
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#endif
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#if 0
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// turn on the op-amp
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EXTEN->EXTEN_CTR |= EXTEN_OPA_EN;
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// select op-amp pos pin: 0 = PA2, 1 = PD7
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EXTEN->EXTEN_CTR |= EXTEN_OPA_PSEL;
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// select op-amp neg pin: 0 = PA1, 1 = PD0
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EXTEN->EXTEN_CTR |= EXTEN_OPA_NSEL;
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#endif
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printf( "ADC Setup\n" );
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SetupTimer1();
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printf( "Timer 1 setup\n" );
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InnerLoop();
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}
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