mirror of
https://github.com/cnlohr/lolra.git
synced 2026-06-17 00:09:31 +00:00
Ok, I am gonna put the timer down for the time being.
This commit is contained in:
@@ -51,8 +51,6 @@ SOFTWARE.
|
||||
#include "ch32v003fun.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "chirpbuff.h"
|
||||
#include "chirpbuffinfo.h"
|
||||
|
||||
#include "LoRa-SDR-Code.h"
|
||||
|
||||
@@ -68,10 +66,6 @@ SOFTWARE.
|
||||
#define SENDBUFF_WORDS (DMA_SIZE_WORDS*2)
|
||||
uint8_t sendbuff[SENDBUFF_WORDS];
|
||||
|
||||
#if !defined( FOUND_PERFECT_DIVISOR )
|
||||
#error Code only written for perfect division right now.
|
||||
#endif
|
||||
|
||||
// Bits are shifted out MSBit first, then to LSBit
|
||||
|
||||
|
||||
@@ -322,6 +316,10 @@ skipreset:\n\
|
||||
void LoopFunction2() __attribute__((aligned(256))) __attribute__((section(".srodata"))) __attribute__ ((noinline));
|
||||
|
||||
__attribute__((section(".sdata"))) __attribute__((aligned(256))) const uint32_t tablef[] = {
|
||||
0x08080808,
|
||||
0x08080809,
|
||||
0x08090809,
|
||||
0x09090908,
|
||||
0x09090909,
|
||||
0x0909090a,
|
||||
0x090a090a,
|
||||
@@ -339,6 +337,18 @@ __attribute__((section(".sdata"))) __attribute__((aligned(256))) const uint32_t
|
||||
0x0c0d0c0d,
|
||||
0x0d0d0d0c,
|
||||
0x0d0d0d0d,
|
||||
0x0d0d0d0d,
|
||||
0x0d0d0d0e,
|
||||
0x0d0e0d0e,
|
||||
0x0e0e0e0d,
|
||||
0x0e0e0e0e,
|
||||
0x0e0e0e0f,
|
||||
0x0e0f0e0f,
|
||||
0x0f0f0f0e,
|
||||
0x0f0f0f0f,
|
||||
0x0f0f0f10,
|
||||
0x0f100f10,
|
||||
0x1010100f,
|
||||
};
|
||||
|
||||
void LoopFunction2()
|
||||
@@ -360,9 +370,9 @@ void LoopFunction2()
|
||||
|
||||
while( here != tail )
|
||||
{
|
||||
uint32_t cp = ((SysTick->CNT>>14)&0xfff)+0x4000;
|
||||
uint32_t cp = ((SysTick->CNT>>14)&0xfff)+0x8030;
|
||||
*(here++) = tablef[run_f>>12];
|
||||
run_f &= 4095;
|
||||
run_f &= (1<<12)-1;
|
||||
run_f += cp;
|
||||
if( here == end )
|
||||
here = start;
|
||||
@@ -444,14 +454,18 @@ int main()
|
||||
TIM1->CCER |= TIM_CC1E;
|
||||
|
||||
// Compare 3 = for output
|
||||
TIM1->CHCTLR2 =
|
||||
TIM_OC3M_0 | TIM_OC3M_1;
|
||||
// Modes:
|
||||
// 0, 1, 2: Nothing
|
||||
// 3: Flip
|
||||
// 4, 5: Nothing
|
||||
// 6, 7: Flipping (Further out)
|
||||
TIM1->CHCTLR2 = TIM_OC3M_1 | TIM_OC3M_0 | TIM_OC3PE | TIM_OC3FE;
|
||||
|
||||
// Compare 1 = for triggering
|
||||
TIM1->CHCTLR1 = TIM_OC1M_2 | TIM_OC1M_1;
|
||||
|
||||
// Set the Capture Compare Register value to 50% initially
|
||||
TIM1->CH3CVR = 4;
|
||||
TIM1->CH3CVR = 0; // ACTUALLY Ignored typically it seems.
|
||||
TIM1->CH1CVR = 0; // This triggers DMA.
|
||||
|
||||
// Enable TIM1 outputs
|
||||
|
||||
Reference in New Issue
Block a user