mirror of
https://github.com/cnlohr/lolra.git
synced 2026-06-15 07:19:25 +00:00
Catch a couple missing updates + add 203 TX
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+1
-1
Submodule ch32v/ch32v003fun updated: 627ddd3a6b...119924c0d9
@@ -81,6 +81,7 @@ volatile uint16_t adc_buffer[ADC_BUFFSIZE];
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void SetupADC()
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{
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// XXX TODO -look into PGA
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// XXX TODO - look into BUFEN and TKITUNE
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// XXX TODO - Look into tag-teaming the ADCs
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// PDA is analog input chl 7
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@@ -193,7 +193,10 @@ void SetupADC()
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while(ADC1->CTLR2 & ADC_CAL);
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// ADC_SCAN: Allow scanning.
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ADC1->CTLR1 = ADC_Pga_64 | ADC_SCAN;
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ADC1->CTLR1 =
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//ADC_SCAN;
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ADC_Pga_16 | ADC_SCAN;
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//ADC_Pga_64 | ADC_SCAN;
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// Turn on DMA
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Binary file not shown.
@@ -0,0 +1,13 @@
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all : flash
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TARGET:=ch32v203tx
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TARGET_MCU:=CH32V203
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CH32V003FUN:=../ch32v003fun/ch32v003fun
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EXTRA_CFLAGS:=-Wno-unused-function -I../../lib
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include $(CH32V003FUN)/ch32v003fun.mk
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flash : cv_flash
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clean : cv_clean
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@@ -0,0 +1,93 @@
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/**
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MIT-like-non-ai-license
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Copyright (c) 2024 Charles Lohr "CNLohr"
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the two following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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In addition the following restrictions apply:
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1. The Software and any modifications made to it may not be used for the
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purpose of training or improving machine learning algorithms, including but not
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limited to artificial intelligence, natural language processing, or data
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mining. This condition applies to any derivatives, modifications, or updates
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based on the Software code. Any usage of the Software in an AI-training dataset
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is considered a breach of this License.
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2. The Software may not be included in any dataset used for training or
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improving machine learning algorithms, including but not limited to artificial
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intelligence, natural language processing, or data mining.
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3. Any person or organization found to be in violation of these restrictions
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will be subject to legal action and may be held liable for any damages
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resulting from such use.
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If any term is unenforcable, other terms remain in-force.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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**/
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#include "ch32v003fun.h"
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#include <stdio.h>
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#define LEDPIN PD6
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int main()
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{
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SystemInit();
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Delay_Ms( 100 );
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funGpioInitAll();
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RCC->APB1PCENR |= RCC_APB1Periph_TIM2;
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// PD4 = T2C1 on 003, PA0 on the 203.
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funPinMode( PA0, GPIO_CFGLR_OUT_50Mhz_AF_PP );
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funPinMode( PA1, GPIO_CFGLR_OUT_50Mhz_AF_PP );
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funPinMode( LEDPIN, GPIO_CFGLR_OUT_50Mhz_PP );
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// Reset TIM2 to init all regs
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RCC->APB1PRSTR |= RCC_APB1Periph_TIM2;
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RCC->APB1PRSTR &= ~RCC_APB1Periph_TIM2;
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TIM2->PSC = 0x0000; // Prescalar
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TIM2->ATRLR = 4; // Max
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TIM2->CHCTLR1 = TIM_OC1M_2 | TIM_OC1M_1 | TIM_OC1PE | TIM_OC1FE;
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TIM2->CTLR1 = TIM_ARPE;
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TIM2->CCER = TIM_CC1E | TIM_CC1P | TIM_CC1NE;
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TIM2->SWEVGR = TIM_UG;
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// Enable TIM2
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TIM2->CTLR1 |= TIM_CEN;
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TIM2->CH1CVR = TIM2->ATRLR/2+1;
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printf( "Setup\n" );
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while(1)
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{
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TIM2->CH1CVR = 2;
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TIM2->CCER = TIM_CC1E | TIM_CC1P;
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funDigitalWrite( LEDPIN, 1 );
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Delay_Us( 2000 );
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TIM2->CCER = TIM_CC1E;
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TIM2->CH1CVR = 2;
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funDigitalWrite( LEDPIN, 0 );
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Delay_Us( 2000 );
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}
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}
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@@ -0,0 +1,9 @@
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#ifndef _FUNCONFIG_H
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#define _FUNCONFIG_H
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#define FUNCONF_USE_DEBUGPRINTF 1
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#define FUNCONF_USE_UARTPRINTF 0
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#define FUNCONF_USE_HSE 1
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#endif
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