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https://github.com/cnlohr/lolra.git
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Update calculator to handle goertzel
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cnlohr
@@ -0,0 +1,374 @@
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/*
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* Single-File-Header for SSD1306 I2C interface
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* 05-07-2023 E. Brombaugh
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*/
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#ifndef _SSD1306_I2C_H
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#define _SSD1306_I2C_H
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#include <string.h>
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// SSD1306 I2C address
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#define SSD1306_I2C_ADDR 0x3c
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// I2C Bus clock rate - must be lower the Logic clock rate
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#define SSD1306_I2C_CLKRATE 1000000
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// I2C Logic clock rate - must be higher than Bus clock rate
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#define SSD1306_I2C_PRERATE 2000000
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// uncomment this for high-speed 36% duty cycle, otherwise 33%
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#define SSD1306_I2C_DUTY
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// I2C Timeout count
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#define TIMEOUT_MAX 100000
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// uncomment this to enable IRQ-driven operation
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//#define SSD1306_I2C_IRQ
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#ifdef SSD1306_I2C_IRQ
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// some stuff that IRQ mode needs
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volatile uint8_t ssd1306_i2c_send_buffer[64], *ssd1306_i2c_send_ptr, ssd1306_i2c_send_sz, ssd1306_i2c_irq_state;
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// uncomment this to enable time diags in IRQ
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//#define IRQ_DIAG
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#endif
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/*
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* init just I2C
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*/
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void ssd1306_i2c_setup(void)
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{
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uint16_t tempreg;
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// Reset I2C1 to init all regs
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RCC->APB1PRSTR |= RCC_APB1Periph_I2C1;
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RCC->APB1PRSTR &= ~RCC_APB1Periph_I2C1;
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// set freq
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tempreg = I2C1->CTLR2;
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tempreg &= ~I2C_CTLR2_FREQ;
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tempreg |= (FUNCONF_SYSTEM_CORE_CLOCK/SSD1306_I2C_PRERATE)&I2C_CTLR2_FREQ;
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I2C1->CTLR2 = tempreg;
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// Set clock config
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tempreg = 0;
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#if (SSD1306_I2C_CLKRATE <= 100000)
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// standard mode good to 100kHz
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tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(2*SSD1306_I2C_CLKRATE))&SSD1306_I2C_CKCFGR_CCR;
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#else
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// fast mode over 100kHz
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#ifndef SSD1306_I2C_DUTY
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// 33% duty cycle
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tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(3*SSD1306_I2C_CLKRATE))&SSD1306_I2C_CKCFGR_CCR;
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#else
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// 36% duty cycle
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tempreg = (FUNCONF_SYSTEM_CORE_CLOCK/(25*SSD1306_I2C_CLKRATE))&I2C_CKCFGR_CCR;
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tempreg |= I2C_CKCFGR_DUTY;
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#endif
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tempreg |= I2C_CKCFGR_FS;
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#endif
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I2C1->CKCFGR = tempreg;
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#ifdef SSD1306_I2C_IRQ
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// enable IRQ driven operation
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NVIC_EnableIRQ(I2C1_EV_IRQn);
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// initialize the state
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ssd1306_i2c_irq_state = 0;
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#endif
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// Enable I2C
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I2C1->CTLR1 |= I2C_CTLR1_PE;
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// set ACK mode
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I2C1->CTLR1 |= I2C_CTLR1_ACK;
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}
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/*
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* error descriptions
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*/
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char *errstr[] =
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{
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"not busy",
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"master mode",
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"transmit mode",
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"tx empty",
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"transmit complete",
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};
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/*
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* error handler
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*/
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uint8_t ssd1306_i2c_error(uint8_t err)
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{
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// report error
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printf("ssd1306_i2c_error - timeout waiting for %s\n\r", errstr[err]);
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// reset & initialize I2C
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ssd1306_i2c_setup();
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return 1;
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}
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// event codes we use
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#define SSD1306_I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
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#define SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
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#define SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
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/*
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* check for 32-bit event codes
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*/
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uint8_t ssd1306_i2c_chk_evt(uint32_t event_mask)
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{
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/* read order matters here! STAR1 before STAR2!! */
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uint32_t status = I2C1->STAR1 | (I2C1->STAR2<<16);
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return (status & event_mask) == event_mask;
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}
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#ifdef SSD1306_I2C_IRQ
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/*
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* packet send for IRQ-driven operation
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*/
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uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz)
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{
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int32_t timeout;
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#ifdef IRQ_DIAG
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GPIOC->BSHR = (1<<(3));
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#endif
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// error out if buffer under/overflow
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if((sz > sizeof(ssd1306_i2c_send_buffer)) || !sz)
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return 2;
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// wait for previous packet to finish
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while(ssd1306_i2c_irq_state);
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#ifdef IRQ_DIAG
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GPIOC->BSHR = (1<<(16+3));
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GPIOC->BSHR = (1<<(4));
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#endif
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// init buffer for sending
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ssd1306_i2c_send_sz = sz;
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ssd1306_i2c_send_ptr = ssd1306_i2c_send_buffer;
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memcpy((uint8_t *)ssd1306_i2c_send_buffer, data, sz);
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// wait for not busy
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timeout = TIMEOUT_MAX;
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while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(0);
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// Set START condition
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I2C1->CTLR1 |= I2C_CTLR1_START;
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// wait for master mode select
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timeout = TIMEOUT_MAX;
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while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(1);
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// send 7-bit address + write flag
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I2C1->DATAR = addr<<1;
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// wait for transmit condition
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timeout = TIMEOUT_MAX;
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while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(2);
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// Enable TXE interrupt
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I2C1->CTLR2 |= I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN;
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ssd1306_i2c_irq_state = 1;
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#ifdef IRQ_DIAG
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GPIOC->BSHR = (1<<(16+4));
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#endif
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// exit
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return 0;
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}
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/*
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* IRQ handler for I2C events
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*/
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void I2C1_EV_IRQHandler(void) __attribute__((interrupt));
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void I2C1_EV_IRQHandler(void)
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{
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uint16_t STAR1, STAR2 __attribute__((unused));
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#ifdef IRQ_DIAG
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GPIOC->BSHR = (1<<(4));
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#endif
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// read status, clear any events
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STAR1 = I2C1->STAR1;
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STAR2 = I2C1->STAR2;
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/* check for TXE */
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if(STAR1 & I2C_STAR1_TXE)
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{
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/* check for remaining data */
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if(ssd1306_i2c_send_sz--)
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I2C1->DATAR = *ssd1306_i2c_send_ptr++;
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/* was that the last byte? */
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if(!ssd1306_i2c_send_sz)
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{
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// disable TXE interrupt
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I2C1->CTLR2 &= ~(I2C_CTLR2_ITBUFEN | I2C_CTLR2_ITEVTEN);
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// reset IRQ state
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ssd1306_i2c_irq_state = 0;
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// wait for tx complete
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while(!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED));
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// set STOP condition
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I2C1->CTLR1 |= I2C_CTLR1_STOP;
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}
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}
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#ifdef IRQ_DIAG
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GPIOC->BSHR = (1<<(16+4));
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#endif
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}
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#else
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/*
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* low-level packet send for blocking polled operation via i2c
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*/
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uint8_t ssd1306_i2c_send(uint8_t addr, uint8_t *data, uint8_t sz)
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{
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int32_t timeout;
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// wait for not busy
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timeout = TIMEOUT_MAX;
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while((I2C1->STAR2 & I2C_STAR2_BUSY) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(0);
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// Set START condition
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I2C1->CTLR1 |= I2C_CTLR1_START;
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// wait for master mode select
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timeout = TIMEOUT_MAX;
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while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_MODE_SELECT)) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(1);
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// send 7-bit address + write flag
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I2C1->DATAR = addr<<1;
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// wait for transmit condition
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timeout = TIMEOUT_MAX;
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while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(2);
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// send data one byte at a time
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while(sz--)
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{
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// wait for TX Empty
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timeout = TIMEOUT_MAX;
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while(!(I2C1->STAR1 & I2C_STAR1_TXE) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(3);
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// send command
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I2C1->DATAR = *data++;
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}
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// wait for tx complete
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timeout = TIMEOUT_MAX;
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while((!ssd1306_i2c_chk_evt(SSD1306_I2C_EVENT_MASTER_BYTE_TRANSMITTED)) && (timeout--));
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if(timeout==-1)
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return ssd1306_i2c_error(4);
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// set STOP condition
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I2C1->CTLR1 |= I2C_CTLR1_STOP;
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// we're happy
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return 0;
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}
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#endif
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/*
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* high-level packet send for I2C
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*/
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uint8_t ssd1306_pkt_send(uint8_t *data, uint8_t sz, uint8_t cmd)
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{
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uint8_t pkt[33];
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/* build command or data packets */
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if(cmd)
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{
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pkt[0] = 0;
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pkt[1] = *data;
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}
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else
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{
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pkt[0] = 0x40;
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memcpy(&pkt[1], data, sz);
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}
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return ssd1306_i2c_send(SSD1306_I2C_ADDR, pkt, sz+1);
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}
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/*
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* init I2C and GPIO
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*/
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uint8_t ssd1306_i2c_init(void)
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{
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// Enable GPIOC and I2C
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RCC->APB1PCENR |= RCC_APB1Periph_I2C1;
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#ifdef CH32V20x
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOB;
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// PB7 is SDA, 10MHz Output, alt func, open-drain
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GPIOB->CFGLR &= ~(0xf<<(4*7));
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GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*7);
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// PB6 is SCL, 10MHz Output, alt func, open-drain
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GPIOB->CFGLR &= ~(0xf<<(4*6));
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GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*6);
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#else
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RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
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// PC1 is SDA, 10MHz Output, alt func, open-drain
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GPIOC->CFGLR &= ~(0xf<<(4*1));
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GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*1);
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// PC2 is SCL, 10MHz Output, alt func, open-drain
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GPIOC->CFGLR &= ~(0xf<<(4*2));
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GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*2);
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#endif
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#ifdef IRQ_DIAG
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// GPIO diags on PC3/PC4
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GPIOC->CFGLR &= ~(0xf<<(4*3));
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GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*3);
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GPIOC->BSHR = (1<<(16+3));
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GPIOC->CFGLR &= ~(0xf<<(4*4));
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GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*4);
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GPIOC->BSHR = (1<<(16+4));
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#endif
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// load I2C regs
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ssd1306_i2c_setup();
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#if 0
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// test if SSD1306 is on the bus by sending display off command
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uint8_t command = 0xAF;
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return ssd1306_pkt_send(&command, 1, 1);
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#else
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return 0;
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#endif
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}
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/*
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* reset is not used for SSD1306 I2C interface
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*/
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void ssd1306_rst(void)
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{
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}
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#endif
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